DESCRIPTION: Many emerging Army applications demand larger format, smaller pixel size IRFPAs to achieve higher resolution and wider fields of view (FOV), without sacrificing existing performance, which has presented a tremendous problem for today’s ROIC technology. The challenge is how to implement sufficient well capacity in small pixel pitch to meet sensitivity and intra-scene dynamic range requirements. Current ROICs are analog with integration capacitor taking up most of pixel area. The ROIC designs are fabricated using the commercially available 250nm or 180nm CMOS foundry process. Capacitors are implemented by laying poly over diffusion, poly over poly, metal over poly or metal over metal with thin layer of oxide grown between the two plates. To achieve higher charge capacitance density, the method of implementing MOS capacitor (using the thinner MOSFET gate oxides) is commonly used. Some foundry processes have processing options to stack MIM (Metal Insulator Metal) capacitors and/or tolerate higher voltage operations (translating into larger voltage swings) which allow for increased charge density. These standard foundry processes typically yield charge capacitive density of 4fF/um2-6fF/um2. As we drive to smaller pixels, SiO2 can no longer meet the ROIC charge storage requirements. This topic seeks to advance the Army’s current IR imaging technology through innovative investigation and development of a suitable high-k dielectric semiconductor material for high performance, high sensitivity cooled IRFPAs. The goal of this effort is achieve charge density >80fF/um2 or >20X of current SiO2 based technology. Particular interest will be given to materials and material growth techniques that are compatible with deposition methods on a silicon readout; however a separate capacitive layer coupled to a readout via 3 dimensional (3D) integration approach that shows high yield potential, reasonable cost to fabricate will be considered.
 

PHASE I: Research, investigate growth techniques and processing methods, to develop a semiconductor high-k dielectric material that is optimized to provide high charge capacitive density per unit area for IRFPA imaging applications through the use of modeling, analysis, empirical testing or fabrication. Innovative materials or material growth techniques that are compatible with deposition methods on a silicon readout are highly desirable. Thin film growth of proposed material along with characterization results would also be highly desirable in phase I effort. Establish working relationship with IR detector vendor to acquire detector arrays for possible phase II effort.
 

PHASE II: Using results of the investigation of phase I, fabricate devices, structures of the proposed materials. Test, and characterize the material’s properties. To show compatibility with current readout technology, design, develop and fabricate a readout with the proposed material. Demonstrate the performance of the high-k dielectric ROIC by mating to IR detector array. Develop and fabricate electronics for an imaging demonstration of the technology.
 

PHASE III DUAL USE APPLICATIONS: Transition the material growth techniques and processes to a production capable technology. The commercialization of this technology includes night driving aid, search and rescue, security, border patrol, firefighting, and a host of other low cost infrared imaging applications.
 

REFERENCES:

1. Wilk, G.D., Wallace, R.M., Anthony, J.M., “High-k gate dielectrics current status and materials properties considerations”, (2001), J. Applied Physics, 89, 5243-5275.
 

2. Groner, M.D., George, S.M., “High-k dielectric grown by atomic layer deposition: capacitor and gate application”, Interlayer Dielectrics for Semiconductor Technologies, chapter 10, 2003.
 

3. DiMeo, Frank, “BST Capacitors for Cryogenic Focal Plane Arrays”, SBIR contract #: DAAL01-97-C-0079, Final Report, June 30, 2000.
 

4. Lupina, G., et al., "Dielectric characteristics of amorphous and crystalline BaHfO3 high-k layers on TiN for memory capacitor application", IEEE Conference: Ultimate Integration of Silicon, 2008. pp. 159-162.